Integrated circuits have become very complex, sometimes including millions of transistors on a single chip. The processes currently used in production of integrated circuits allow for using very small transistors, which makes their design even more complex. It is therefore important to verify correctness of the design of integrated circuits.
Many elements of integrated circuits are synchronous elements which are timed by a clock signal. The faster the clock signal operates, the more operations are performed by the integrated circuit within a given time. There are, however, limitations on the speed at which circuits can operate and the clock signal therefore has to have a rate lower than the fastest rate allowed by the circuit. Different circuits are therefore designed at different rates. Some integrated circuits include sections which operate at different clock rates. A point at which circuits having different clock rates are interconnected is referred to as a clock domain crossing (CDC). Incorrect design of clock domain crossings may result in the entire integrated circuit not operating properly.
A paper titled: “A Comprehensive Approach to Modeling, Characterizing and Optimizing for Metastability in FPGAs”, by Betz et al., the disclosure of which is incorporated herein by reference, presents a function for calculating a mean time between synchronization failures (MTBF) and requires that the MTBF be sufficiently long to avoid synchronization failures.
Integrated circuits are generally defined in a hardware definition language (HDL), which is compiled and converted into a circuit layout. In some cases, portions of the circuit are represented in the circuit description by a high level definition which does not include lower level details. Such portions are referred to as black-boxes. Black-boxes are used, for example, when it is desired to generate the high level circuit description before the details of the black-box are ready and/or when the black-box is purchased from an external vendor.
US patent publication 2010/0180240, to J. D. Davis, M. Budiu, H. Kannan, titled: Optimizing system-on-a-chip using the dynamic critical path, the disclosure of which is incorporated herein by reference, describes critical path optimization which performs simulations of circuits including black-boxes to assess latency or power, based on user provided information on the black-boxes, although the internal structure of the black-boxes is unknown.
U.S. Pat. No. 7,984,404 to K. T. Do, H. Kim, H. S. Son, Postech Academy-Industry Foundation, titled: “Black box timing modeling method and computer system for latch-based sub-system”, the disclosure of which is incorporated herein by reference, discusses providing timing modeling (e.g. setup timing) for black-boxes, allowing faster timing analysis.